Stacking memory onto processors (CoWoS, HBM) — the physical bottleneck on AI chip supply.
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Packaging is the step that turns finished silicon into a usable part — stacking memory onto logic, connecting dies, and managing the heat and power that result. For AI accelerators it has repeatedly been the actual bottleneck, more than the processor itself.
It used to be the least glamorous step in chipmaking, treated as commodity assembly. High-bandwidth memory changed that: if you cannot package it, you cannot ship it, however many wafers you have.
What moves it: packaging capacity expansions, yield on new stacking techniques, and accelerator production targets.
The Weekly Pulse covers Advanced Packaging alongside every other sector — one email, Sunday, free.
A packaging technique that places logic and memory dies side by side on a shared substrate, connecting them with far more bandwidth than a conventional package allows. Capacity for it has been a widely tracked constraint on accelerator supply.
A processor is not shippable until memory is attached and the part is assembled. If packaging capacity is smaller than wafer capacity, packaging sets the ceiling.
An outsourced semiconductor assembly and test provider — a specialist that packages and tests chips for companies that do not do it in-house.